Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7271083 | One-transistor random access memory technology compatible with metal gate process | Kuo-Chi Tu, Chung-Yi Chen, C. Y. Shen, Chun-Yao Chen, Hsiang-Fan Lee | 2007-09-18 |
| 7091543 | Embedded dual-port DRAM process | Ming-Hsiang Chiang, Wen-Chuan Chiang, Dennis Sinitsky | 2006-08-15 |
| 6794254 | Embedded dual-port DRAM process | Ming-Hsiang Chiang, Wen-Chuan Chiang, Dennis Sinitsky | 2004-09-21 |
| 6713406 | Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devices | Chu-Yun Fu | 2004-03-30 |
| 6670664 | Single transistor random access memory (1T-RAM) cell with dual threshold voltages | Dennis Sinitsky, Chen-Jong Wang, Wen-Chaun Chiang | 2003-12-30 |
| 6661049 | Microelectronic capacitor structure embedded within microelectronic isolation region | Chen-Jong Wang, Chung-Wei Chang | 2003-12-09 |
| 6661050 | Memory cell structure with trench capacitor and method for fabrication thereof | Chen-Jong Wang, Chung-Wei Chang | 2003-12-09 |
| 6638813 | Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell | Chen-Jong Wang, Chung-Wei Chang, Wen-Chuan Chiang, Wen-Cheng Chen, Kuo-Ching Huang | 2003-10-28 |
| 6620679 | Method to integrate high performance 1T ram in a CMOS process using asymmetric structure | Chen-Jong Wang, Dennis Sinitsky | 2003-09-16 |
| 6613690 | Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers | Chung-Wei Chang, Chen-Jong Wang, Min-Hsiang Chiang, Chi-Hsing Lo | 2003-09-02 |
| 6569732 | Integrated process sequence allowing elimination of polysilicon residue and silicon damage during the fabrication of a buried stack capacitor structure in a SRAM cell | Min-Hsiung Chiang, Chung-Wei Chang | 2003-05-27 |
| 6436762 | Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins | Tse-Liang Ying, Min-Hsiung Chiang, Hsiao-Hui Tseng, Chung-Wei Chang | 2002-08-20 |
| 6383863 | Approach to integrate salicide gate for embedded DRAM devices | Min-Hsiung Chiang, Hsiao-Hui Tseng, Hsien-Yuan Chang, Chung-Wei Chang | 2002-05-07 |
| 6376294 | Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process | Wen-Chuan Chiang, Wen-Cheng Chen, Chen-Jong Wang | 2002-04-23 |
| 6306767 | Self-aligned etching method for forming high areal density patterned microelectronic structures | Tse-Liang Ying, Wen-Chuan Chiang, Ming-Hsiang Chiang | 2001-10-23 |
| 6242757 | Capacitor circuit structure for determining overlay error | Wen-Jye Chung | 2001-06-05 |
| 6207492 | Common gate and salicide word line process for low cost embedded DRAM devices | Tse-Liang Ying, Chen-Jong Wang, Kevin Chiang | 2001-03-27 |
| 6143621 | Capacitor circuit structure for determining overlay error | Wen-Jye Chung | 2000-11-07 |