Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10509883 | Method for layout generation with constrained hypergraph partitioning | Tsun-Yu Yang, Wei Hu, Hsien-Hsin Sean Lee, Po-Cheng Pan, Hung-Wen Huang +2 more | 2019-12-17 |
| 10346576 | Electromigration sign-off methodology | Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang | 2019-07-09 |
| 10162244 | Configurable heating device | Hui Yu Lee | 2018-12-25 |
| 10163787 | Semiconductor structure | Hui Yu Lee, Feng-Wei Kuo, Yi-Kan Cheng | 2018-12-25 |
| 10157252 | Method and apparatus of a three dimensional integrated circuit | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Yi-Kan Cheng | 2018-12-18 |
| 10095827 | Method of manufacturing a semiconductor device | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Yi-Kan Cheng | 2018-10-09 |
| 10083257 | Method, system and computer program product for generating simulation sample | Chin-Cheng Kuo, Wei Min Chan, Wei Hu | 2018-09-25 |
| 10042967 | Electromigration sign-off methodology | Yu-Tseng Hsien, Chin-Shen Lin, Ching-Shun Yang | 2018-08-07 |
| 9996643 | Integrated circuit modeling method using resistive capacitance information | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Ching-Shun Yang | 2018-06-12 |
| 9934352 | Method and system for manufacturing a semiconductor device | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Yi-Kan Cheng | 2018-04-03 |
| 9753895 | Method for process variation analysis of an integrated circuit | Chin-Cheng Kuo, Kmin Hsu, Wei Hu, Wei Min Chan | 2017-09-05 |
| 9748228 | Structure and method for cooling three-dimensional integrated circuits | Hui Yu Lee, Chi-Wen Chang, Yi-Kan Cheng | 2017-08-29 |
| 9698099 | Semiconductor structure having a plurality of conductive paths | Hui Yu Lee, Feng-Wei Kuo, Yi-Kan Cheng | 2017-07-04 |
| 9519735 | Method of failure analysis | Chin-Cheng Kuo, Kmin Hsu, Wei Hu, Wei Min Chan | 2016-12-13 |
| 9418200 | Integrated circuit design system and method of generating proposed device array layout | Ching-Yu Chai, Chin-Sheng Chen, Wei Hu | 2016-08-16 |
| 9411926 | Method of performing circuit simulation and generating circuit layout | Hui Yu Lee, Feng-Wei Kuo, Simon Yi-Hung Chen | 2016-08-09 |
| 9367654 | Variation modeling | Chi-Wen Chang, Hui Yu Lee, Yi-Kan Cheng, Chin-Hua Wen, Wen-Shen Chou | 2016-06-14 |
| 9355205 | Method and apparatus of a three dimensional integrated circuit | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Yi-Kan Cheng | 2016-05-31 |
| 9348965 | Parasitic component library and method for efficient circuit design and simulation using the same | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Tao Wen Chung, Yi-Kan Cheng | 2016-05-24 |
| 9213797 | Method, system and computer program product for designing semiconductor device | Chi-Wen Chang, Hui Yu Lee, Ya Yun Liu, Yi-Kan Cheng | 2015-12-15 |
| 9129082 | Variation factor assignment | Chi-Wen Chang, Hui Yu Lee, Yi-Kan Cheng, Chin-Hua Wen, Wen-Shen Chou | 2015-09-08 |
| 9122833 | Method of designing fin field effect transistor (FinFET)-based circuit and system for implementing the same | Chin-Sheng Chen, Tsun-Yu Yang, Wei Hu, Ching-Shun Yang, Yi-Kan Cheng | 2015-09-01 |
| 9092589 | Integrated circuit design flow with device array layout generation | Ching-Yu Chai, Chin-Sheng Chen, Wei Hu | 2015-07-28 |
| 9053255 | Semiconductor structure and method of generating masks for making integrated circuit | Hui Yu Lee, Feng-Wei Kuo, Yi-Kan Cheng | 2015-06-09 |
| 8943454 | In-phase grouping for voltage-dependent design rule | Chih Chi Hsiao, Jill Liu, Wei Hu, Yu-Ren Chen, Kuo-Ji Chen +2 more | 2015-01-27 |