Issued Patents All Time
Showing 51–75 of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11189356 | One-time-programmable memory | Yih Wang | 2021-11-30 |
| 11183261 | Test device for memory, method for detecting hardware failure in memory device, and test apparatus of memory array | Ku-Feng Lin, Yih Wang | 2021-11-23 |
| 11152057 | SRAM memory | Hidehiro Fujiwara, Cheng Chun Dai, Chih-Yu Lin, Yen-Huei Chen | 2021-10-19 |
| 11107530 | Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells | Perng-Fei Yuh, Yih Wang, Ku-Feng Lin, Jui-Che Tsai, Fu-An Wu | 2021-08-31 |
| 10943667 | Memory device | Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2021-03-09 |
| 10642685 | Cache memory and processor system | Kazutaka Ikegami, Shinobu Fujita | 2020-05-05 |
| 10592163 | Controlling write pulse width to non-volatile memory based on free space of a storage | Shinobu Fujita | 2020-03-17 |
| 10585587 | Memory control circuitry, memory system and processor system | Shinobu Fujita | 2020-03-10 |
| 10557751 | Method, program, cumulative received-light amount estimation apparatus, and health care system using solar radiation amount information corresponding to position information of a device and time information | Yuri FUJIWARA | 2020-02-11 |
| 10528270 | Memory system having nonvolatile memory and volatile memory and processor system | Keiko Abe, Susumu Takeda, Kumiko Nomura, Shinobu Fujita | 2020-01-07 |
| 10521134 | Memory system | Shinobu Fujita | 2019-12-31 |
| 10496546 | Cache memory and processor system | Tetsufumi Tanamoto, Kazutaka Ikegami, Shinobu Fujita | 2019-12-03 |
| 10481975 | Memory system | Daisuke Saida, Keiko Abe, Shinobu Fujita | 2019-11-19 |
| 10431303 | Resistance change type memory including write control circuit to control write to variable resistance element | Takayuki Nozaki, Yoshishige Suzuki, Shinji Yuasa, Yoichi Shiota, Takurou Ikeura +1 more | 2019-10-01 |
| 10423536 | Memory system with plural nonvolatile memories having different access sizes, different speeds using address conversion information to access one memory by converting an address to access another memory | Shinobu Fujita | 2019-09-24 |
| 10360100 | Cache memory system and processor system | Shinobu Fujita | 2019-07-23 |
| 10360151 | Cache memory system including first cache memory and second cache memory having multiple regions with different access speed and processor system | Shinobu Fujita | 2019-07-23 |
| 10283180 | Nonvolatile resistance changing semiconductor memory using first and second writing operations | Satoshi Takaya, Keiko Abe, Shinobu Fujita | 2019-05-07 |
| 10249352 | Memory device and memory system | Satoshi Takaya, Shinobu Fujita | 2019-04-02 |
| 10236062 | Processor | Kazutaka Ikegami, Shinobu Fujita, Keiko Abe, Kumiko Nomura | 2019-03-19 |
| 10141038 | Computer system and memory device | Kazutaka Ikegami, Keiko Abe | 2018-11-27 |
| 10120750 | Cache memory, error correction circuitry, and processor system | Susumu Takeda, Kazutaka Ikegami, Shinobu Fujita | 2018-11-06 |
| 10102894 | Magnetic memory | Naoharu Shimomura, Tomoaki Inokuchi, Katsuhiko Koui, Yuuzo Kamiguchi, Kazutaka Ikegami +1 more | 2018-10-16 |
| 10083729 | Magnetic memory and memory system | Shinobu Fujita | 2018-09-25 |
| 10042725 | Memory control circuit, cache memory and memory control method | Shinobu Fujita, Keiko Abe | 2018-08-07 |