Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9768256 | Formation of dislocations in source and drain regions of FinFET devices | Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee | 2017-09-19 |
| 9620386 | Methods of annealing after deposition of gate layers | Chun Hsiung Tsai, Xiong-Fei Yu, Yu-Lien Huang | 2017-04-11 |
| 9590101 | FinFET with multiple dislocation planes and method for forming the same | Chih-Hsiang Huang | 2017-03-07 |
| 9537010 | Semiconductor device structure and method for forming the same | Tsan-Chun Wang, Ziwei Fang, Chien-Tai Chan, Huicheng Chang | 2017-01-03 |
| 9412870 | Device with engineered epitaxial region and methods of making same | King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai | 2016-08-09 |
| 9373704 | Multiple-gate semiconductor device and method | Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Hsien-Chin Lin | 2016-06-21 |
| 9362278 | FinFET with multiple dislocation planes and method for forming the same | Chih-Hsiang Huang | 2016-06-07 |
| 9293534 | Formation of dislocations in source and drain regions of FinFET devices | Chun Hsiung Tsai, Wei-Yuan Lu, Chien-Tai Chan, Wei-Yang Lee | 2016-03-22 |
| 9281356 | Integrated circuit resistor | King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Kuo-Feng Yu | 2016-03-08 |
| 9117843 | Device with engineered epitaxial region and methods of making same | King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai | 2015-08-25 |
| 9105664 | Method for enhancing channel strain | Ming-Lung Cheng, Yen-Chun Lin | 2015-08-11 |
| 8951875 | Semiconductor structure | King-Yuen Wong, Ming-Lung Cheng, Chien-Tai Chan, Chung-Cheng Wu | 2015-02-10 |
| 8921946 | Integrated circuit resistor | King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Kuo-Feng Yu | 2014-12-30 |
| 8895383 | Multiple-gate semiconductor device and method | Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Hsien-Chin Lin | 2014-11-25 |
| 8809175 | Methods of anneal after deposition of gate layers | Chun Hsiung Tsai, Xiong-Fei Yu, Yu-Lien Huang | 2014-08-19 |
| 8785286 | Techniques for FinFET doping | Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh | 2014-07-22 |
| 8759943 | Transistor having notched fin structure and method of making the same | Chih-Hung Tseng, Chien-Tai Chan, Chia-Pin Lin, Li-Wen Weng, An-Shen Chang +1 more | 2014-06-24 |
| 8753980 | Rapid thermal annealing to reduce pattern effect | Chun Hsiung Tsai, Chii-Ming Wu | 2014-06-17 |
| 8729627 | Strained channel integrated circuit devices | Ming-Lung Cheng, Yen-Chun Lin | 2014-05-20 |
| 8703593 | Techniques for FinFET doping | Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh | 2014-04-22 |
| 8557692 | FinFET LDD and source drain implant technique | Chun Hsiung Tsai, Chien-Chang Su, Tsung-Hung Li, Wen-Sheh Huang | 2013-10-15 |
| 8426923 | Multiple-gate semiconductor device and method | Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Hsien-Chin Lin | 2013-04-23 |
| 8404538 | Device with self aligned stressor and method of making same | Kao-Ting Lai, Hsien-Hsin Lin, Yuan-Ching Peng, Chi-Hsi Wu | 2013-03-26 |
| 8383513 | Asymmetric rapid thermal annealing to reduce pattern effect | Chun Hsiung Tsai, Chii-Ming Wu | 2013-02-26 |
| 8357579 | Methods of forming integrated circuits | King-Yuen Wong, Ming-Lung Cheng, Chien-Tai Chan, Chung-Cheng Wu | 2013-01-22 |