Issued Patents All Time
Showing 26–50 of 282 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11568122 | Integrated circuit fin layout method | Po-Hsiang Huang, Fong-Yuan Chang, Chih-Hsin Ko, Sheng-Hsiung Chen, Li-Chun Tien +1 more | 2023-01-31 |
| 11532612 | Inter-level connection for multi-layer structures | Yi-Tang Lin, Neng-Kuo Chen | 2022-12-20 |
| 11508627 | Method of metal gate formation and structures formed by the same | Yi-Jing Lee, Ya-Yun Cheng, Hau-Yu Lin, I-Sheng Chen, Chia-Ming Hsu +1 more | 2022-11-22 |
| 11502186 | FinFET device having a channel defined in a diamond-like shape semiconductor structure | You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko | 2022-11-15 |
| 11450571 | Method for manufacturing semiconductor structure | Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Chung-Cheng Wu | 2022-09-20 |
| 11450661 | Forming STI regions to separate semiconductor Fins | Chih-Yu Hsu, Yi-Tang Lin, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu +1 more | 2022-09-20 |
| 11437493 | Gate spacer structures and methods for forming the same | Chun Hsiung Tsai, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More, Yu-Ming Lin | 2022-09-06 |
| 11437517 | Semiconductor structures and methods with high mobility and high energy bandgap materials | Cheng-Hsien Wu, Chih-Hsin Ko | 2022-09-06 |
| 11404322 | Method of manufacturing a semiconductor device | Chun Hsiung Tsai, Yu-Ming Lin, Kuo-Feng Yu, Ming-Hsi Yeh, Shahaji B. More +2 more | 2022-08-02 |
| 11362000 | Wrap-around contact on FinFET | Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin +5 more | 2022-06-14 |
| 11329139 | Semiconductor device with reduced trap defect and method of forming the same | Chun Hsiung Tsai, Kuo-Feng Yu, Yu-Ming Lin | 2022-05-10 |
| 11233140 | Semiconductor device and manufacturing method thereof | Chun Hsiung Tsai, Kuo-Feng Yu, Yi-Tang Lin, Yu-Ming Lin | 2022-01-25 |
| 11232943 | Method and structure for semiconductor interconnect | Ru-Shang Hsiao, Chun Hsiung Tsai | 2022-01-25 |
| 11201205 | Interconnect layout for semiconductor device | Chun Hsiung Tsai, Shahaji B. More, Yu-Ming Lin | 2021-12-14 |
| 11177368 | Semiconductor arrangement | Wei-Chieh Chen, Hao-Hsiung Lin, Shu-Han Chen, You-Ru Lin, Cheng-Hsien Wu +1 more | 2021-11-16 |
| 11158725 | Fin structure of fin field effect transistor | Feng Yuan, Hung-Ming Chen, Tsung-Lin Lee, Chang-Yun Chang | 2021-10-26 |
| 11158719 | Method of manufacturing semiconductor devices and semiconductor devices | Yi-Jing Lee, Chih-Shin Ko | 2021-10-26 |
| 11133222 | Method for manufacturing semiconductor structure | Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Yu-Ming Lin | 2021-09-28 |
| 11080453 | Integrated circuit fin layout method, system, and structure | Po-Hsiang Huang, Sheng-Hsiung Chen, Chih-Hsin Ko, Fong-Yuan Chang, Li-Chun Tien +1 more | 2021-08-03 |
| 11075108 | Mechanism for FinFET well doping | Chun Hsiung Tsai, Yan-Ting Lin | 2021-07-27 |
| 10978451 | Complimentary metal-oxide-semiconductor (CMOS) with low contact resistivity and method of forming same | Chih-Hsin Ko, Cheng-Hsien Wu, Ding-Kang Shih, Hau-Yu Lin | 2021-04-13 |
| 10971594 | Semiconductor device having modified profile metal gate | Yu-Lien Huang, Chi-Wen Liu, Ming-Huan Tsai, Zhao-Cheng Chen | 2021-04-06 |
| 10943995 | Self-aligned passivation of active regions | Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai | 2021-03-09 |
| 10916469 | Systems and methods for a semiconductor structure having multiple semiconductor-device layers | Yi-Tang Lin, Chun Hsiung Tsai | 2021-02-09 |
| 10879065 | III-V compound semiconductors in isolation regions and method forming same | Chih-Hsin Ko, Cheng-Hsien Wu | 2020-12-29 |