CL

Chun-Chieh Lin

TSMC: 80 patents #371 of 12,232Top 4%
NM Novatek Microelectronics: 9 patents #96 of 986Top 10%
Apple: 3 patents #7,422 of 18,612Top 40%
AO Au Optronics: 3 patents #977 of 2,945Top 35%
UM United Microelectronics: 3 patents #1,523 of 4,560Top 35%
Oracle: 2 patents #5,522 of 14,854Top 40%
AT Advanced Ion Beam Technology: 2 patents #24 of 69Top 35%
AE Advanced Semiconductor Engineering: 2 patents #403 of 1,073Top 40%
AC Asustek Computer: 2 patents #383 of 1,430Top 30%
RP Revlon Consumer Products: 2 patents #92 of 254Top 40%
GL Genesys Logic: 1 patents #29 of 66Top 45%
📍 Taichung, NY: #3 of 26 inventorsTop 15%
Overall (All Time): #11,198 of 4,157,543Top 1%
113
Patents All Time

Issued Patents All Time

Showing 101–113 of 113 patents

Patent #TitleCo-InventorsDate
7057237 Method for forming devices with multiple spacer widths Howard Chih-Hao Wang, Chenming Hu 2006-06-06
7045847 Semiconductor device with high-k gate dielectric Wen-Chin Lee, Chenming Hu, Shang-Chih Chen, Chih-Hao Wang, Fu-Liaog Yang +1 more 2006-05-16
6963114 SOI MOSFET with multi-sided source/drain silicide 2005-11-08
6955952 Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement Yee-Chia Yeo, Fu-Liang Yang, Mong-Song Liang, Chenming Hu 2005-10-18
6953972 Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer Yee-Chia Yeo, Fu-Liang Yang, Chen Ming Hu 2005-10-11
6921913 Strained-channel transistor structure with lattice-mismatched zone Yee-Chia Yeo, Wen-Chin Lee, Chenming Hu 2005-07-26
6875655 Method of forming DRAM capacitors with protected outside crown surface for more robust structures Lan-Lin Chao, Chia-Hui Lin, Fu-Liang Yang, Chia-Shiung Tsai, Chanming Hu 2005-04-05
6816748 Smart automatic recording system and method for monitoring wafer fragmentation Ting Chen, Wen-Chin Kuo, Yong-Sen Liao 2004-11-09
6812116 Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance Chien-Chao Huang, Yee-Chia Yeo, Kuo-Nan Yang, Chenming Hu 2004-11-02
6703271 Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer Yee-Chia Yeo, Fu-Liang Yang, Chen Ming Hu 2004-03-09
6656844 Method of forming a protected crown capacitor structure utilizing the outside crown surface to increase capacitance Wong-Cheng Shih 2003-12-02
D420171 Nail buffer with panels Kurt Alan Fauerbach, Rachel Clark Stewart 2000-02-01
D418632 Nail buffer with numbered side panels Kurt Alan Fauerbach, Rachel Clark Stewart 2000-01-04