Issued Patents All Time
Showing 26–50 of 137 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11923293 | Barrier structure on interconnect wire to increase processing window for overlying via | Hsin-Chieh Yao, Chung-Ju Lee, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai | 2024-03-05 |
| 11915943 | Methods of etching metals in semiconductor devices | Wei-Hao Liao, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee | 2024-02-27 |
| 11882871 | Detachable atomizing device and container thereof | Chen-Hsiang Sang, Liang-Rern Kung, Wei CAI, JO-LING WU, Shu-Pin Hsieh | 2024-01-30 |
| 11856866 | Magnetic tunnel junction devices | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chung-Ju Lee | 2023-12-26 |
| 11854965 | Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability | Yu-Teng Dai, Chung-Ju Lee, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao | 2023-12-26 |
| 11854836 | Semiconductor device | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chung-Ju Lee | 2023-12-26 |
| 11849645 | Integrated circuit | Wei-Hao Liao, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee | 2023-12-19 |
| 11848207 | Method and structure of cut end with self-aligned double patterning | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chung-Ju Lee | 2023-12-19 |
| 11842966 | Integrated chip with inter-wire cavities | Hsin-Chieh Yao, Chung-Ju Lee, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai +2 more | 2023-12-12 |
| 11842924 | Dual etch-stop layer structure | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee | 2023-12-12 |
| 11837546 | Self-aligned cavity strucutre | Wei-Hao Liao, Chung-Ju Lee, Hsi-Wen Tien, Yu-Teng Dai | 2023-12-05 |
| 11798910 | Self-aligned interconnect structure | Hsin-Chieh Yao, Chung-Ju Lee, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2023-10-24 |
| 11798840 | Self-assembled dielectric on metal RIE lines to increase reliability | Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee | 2023-10-24 |
| 11776845 | Semiconductor arrangement and method of making | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chung-Ju Lee | 2023-10-03 |
| 11756884 | Interconnection structure and methods of forming the same | Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee | 2023-09-12 |
| 11728271 | Structure and method for a low-K dielectric with pillar-type air-gaps | Chung-Ju Lee, Tien-I Bao | 2023-08-15 |
| 11723282 | Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via | Wei-Hao Liao, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee | 2023-08-08 |
| 11688782 | Semiconductor structure and method for forming the same | Wei-Hao Liao, Hsi-Wen Tien, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee | 2023-06-27 |
| 11652054 | Dielectric on wire structure to increase processing window for overlying via | Hsin-Chieh Yao, Chung-Ju Lee, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao | 2023-05-16 |
| 11631639 | Method of fabricating self-aligned via structures | Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee | 2023-04-18 |
| 11569096 | Semiconductor device | Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chung-Ju Lee | 2023-01-31 |
| 11569127 | Double patterning approach by direct metal etch | Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee | 2023-01-31 |
| 11563167 | Structure and method for an MRAM device with a multi-layer top electrode | Wei-Hao Liao, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee | 2023-01-24 |
| 11521896 | Selective deposition of a protective layer to reduce interconnect structure critical dimensions | Hsi-Wen Tien, Chung-Ju Lee, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao | 2022-12-06 |
| 11521970 | Semiconductor device and a method for fabricating the same | Hsiang-Ku Shen, Hui-Chi Chen, Jeng-Ya David Yeh | 2022-12-06 |