Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7437340 | Designing of a logic circuit for testability | Hiroshi Date, Michiaki Muraoka | 2008-10-14 |
| 6708315 | Method of design for testability, method of design for integrated circuits and integrated circuits | Masayoshi Yoshimura | 2004-03-16 |
| 6651206 | Method of design for testability, test sequence generation method and semiconductor integrated circuit | Mitsuyasu Ohta | 2003-11-18 |
| 6510535 | Method of design for testability for integrated circuits | Toshihiro Hiraoka | 2003-01-21 |
| 6449743 | Method of generating test sequences | — | 2002-09-10 |
| 6292915 | Method of design for testability and method of test sequence generation | Tomoo Inoue, Hideo Fujiwara | 2001-09-18 |
| 6271677 | Semiconductor integrated circuit and method for testing the semiconductor integrated circuit | Mitsuyasu Ohta, Sadami Takeoka, Osamu Ichikawa | 2001-08-07 |
| 6253343 | Method of design for testability test sequence generation method and semiconductor integrated circuit | Mitsuyasu Ohta | 2001-06-26 |
| 6185721 | Method of design for testability at RTL and integrated circuit designed by the same | — | 2001-02-06 |
| 6016564 | Method of design for testability, method of design for avoiding bus error and integrated circuit | — | 2000-01-18 |
| 5748646 | Design-for-testability method for path delay faults and test pattern generation method for path delay faults | — | 1998-05-05 |
| 5737341 | Method of generating test sequence and apparatus for generating test sequence | — | 1998-04-07 |
| 5483543 | Test sequence generation method | Akira Motohara, Mitsuyasu Ohta | 1996-01-09 |
| 5319647 | Method and apparatus for performing automatic test pattern generation | Akira Motohara | 1994-06-07 |
| 5305328 | Method of test sequence generation | Akira Motohara, Mitsuyasu Ohta | 1994-04-19 |