Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7284134 | ID installable LSI, secret key installation method, LSI test method, and LSI development method | Makoto Fujiwara | 2007-10-16 |
| 7281136 | LSI design method and verification method | Kentaro Shiomi, Makoto Fujiwara, Toshiyuki Yokoyama, Katsuya Fujimura | 2007-10-09 |
| 7148503 | Semiconductor device, function setting method thereof, and evaluation method thereof | Katsuya Fujimura, Toshiyuki Yokoyama, Kentaro Shiomi | 2006-12-12 |
| 7017135 | Method of designing semiconductor integrated circuit utilizing a scan test function | Sadami Takeoka, Takahiro Ichinomiya | 2006-03-21 |
| 6886150 | Method for designing integrated circuit device | Makoto Fujiwara, Toshiyuki Yokoyama | 2005-04-26 |
| 6671857 | Method of designing integrated circuit device using common parameter at different design levels, and database thereof | Miwaka Takahashi, Toshiyuki Yokoyama, Masahiro Ohashi | 2003-12-30 |
| 6668337 | Method for designing integrated circuit based on the transaction analyzing model | Miwaka Takahashi, Osamu Ogawa | 2003-12-23 |
| 6523157 | Method for designing integrated circuit device and database for design of integrated circuit device | Miwaka Takahashi | 2003-02-18 |
| 6415416 | Method for improving the efficiency of designing a system-on-chip integrated circuit device | Makoto Fujiwara, Toshiyuki Yokoyama | 2002-07-02 |
| 6282506 | Method of designing semiconductor integrated circuit | Sadami Takeoka, Takahiro Ichinomiya | 2001-08-28 |
| 5894482 | Semiconductor integrated circuit with a testable block | — | 1999-04-13 |
| 5729553 | Semiconductor integrated circuit with a testable block | — | 1998-03-17 |
| 5617427 | Method for generating test sequences for detecting faults in target scan logical blocks | Mitsuyasu Ohta | 1997-04-01 |
| 5483543 | Test sequence generation method | Toshinori Hosokawa, Mitsuyasu Ohta | 1996-01-09 |
| 5430736 | Method and apparatus for generating test pattern for sequential logic circuit of integrated circuit | Sadami Takeoka | 1995-07-04 |
| 5319647 | Method and apparatus for performing automatic test pattern generation | Toshinori Hosokawa | 1994-06-07 |
| 5305328 | Method of test sequence generation | Toshinori Hosokawa, Mitsuyasu Ohta | 1994-04-19 |