Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6282630 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-08-28 |
| 6272619 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-08-07 |
| 6263423 | System and method for translating non-native instructions to native instructions for processing on a host processor | Brett W. Coon, Le Trong Nguyen, Johannes Wang | 2001-07-17 |
| 6256720 | High performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2001-07-03 |
| 6249167 | Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the same | Yasuhiro Oguchi | 2001-06-19 |
| 6233596 | Multiple sum-of-products circuit and its use in electronic equipment and microcomputers | Satoshi Kubota, Makoto Kudo | 2001-05-15 |
| 6167505 | Data processing circuit with target instruction and prefix instruction | Satoshi Kubota, Makoto Kudo | 2000-12-26 |
| 6128723 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-10-03 |
| 6101594 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-08-08 |
| 6092181 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-07-18 |
| 6038653 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-03-14 |
| 6038654 | High performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-03-14 |
| 5987593 | System and method for handling load and/or store operations in a superscalar microprocessor | Cheryl D. Senter, Johannes Wang, Brett W. Coon, Le Trong Nguyen | 1999-11-16 |
| 5983334 | Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instructions translating from in-order CISC instructions | Brett W. Coon, Le Trong Nguyen, Johannes Wang | 1999-11-09 |
| 5961629 | High performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1999-10-05 |
| 5832292 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1998-11-03 |
| 5828861 | System and method for reducing the critical path in memory control unit and input/output control unit operations | Cheng-Long Tang | 1998-10-27 |
| 5689720 | High-performance superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1997-11-18 |
| 5619666 | System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor | Brett W. Coon, Le Trong Nguyen, Johannes Wang | 1997-04-08 |
| 5560032 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1996-09-24 |
| 5546552 | Method for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor | Brett W. Coon, Le Trong Nguyen, Johannes Wang | 1996-08-13 |
| 5539911 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +3 more | 1996-07-23 |
| 5481685 | RISC microprocessor architecture implementing fast trap and exception state | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +1 more | 1996-01-02 |
| 5448705 | RISC microprocessor architecture implementing fast trap and exception state | Le Trong Nguyen, Derek J. Lentz, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang +1 more | 1995-09-05 |
| 5438668 | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer | Brett W. Coon, Le Trong Nguyen, Johannes Wang | 1995-08-01 |