Issued Patents All Time
Showing 51–60 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5778434 | System and method for processing multiple requests and out of order returns | Le Trong Nguyen | 1998-07-07 |
| 5754800 | Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption | Derek J. Lentz, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 1998-05-19 |
| 5689720 | High-performance superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Johannes Wang +3 more | 1997-11-18 |
| 5604865 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | Derek J. Lentz, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 1997-02-18 |
| 5560032 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Johannes Wang +3 more | 1996-09-24 |
| 5539911 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Johannes Wang +3 more | 1996-07-23 |
| 5481685 | RISC microprocessor architecture implementing fast trap and exception state | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Johannes Wang +1 more | 1996-01-02 |
| 5448705 | RISC microprocessor architecture implementing fast trap and exception state | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Johannes Wang +1 more | 1995-09-05 |
| 5440752 | Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU | Derek J. Lentz, Te-Li Lau, Cheng-Long Tang, Le Trong Nguyen | 1995-08-08 |
| 5309560 | Data selection device | Sachiyuki Abe, Hisao Sato, Hiroaki Nasu | 1994-05-03 |