Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837431 | 3D semicircular vertical NAND string with recessed inactive semiconductor channel sections | Masatoshi Nishikawa, Masafumi Miyamoto | 2017-12-05 |
| 9818798 | Vertical thin film transistors in non-volatile storage systems | Naoki Takeguchi | 2017-11-14 |
| 9728499 | Set of stepped surfaces formation for a multilevel interconnect structure | Seiji Shimabukuro, Michiaki Sano, Naoki Takeguchi | 2017-08-08 |
| 9691778 | Multiheight contact via structures for a multilevel interconnect structure | Keisuke Izumi, Ryo Taura, Kentaro Sera, Akio Yanai | 2017-06-27 |
| 9601508 | Blocking oxide in memory opening integration scheme for three-dimensional memory structure | Jongsun Sel, Chan Park, Atsushi Suyama, Frank Yu, Hiroyuki Ogawa +6 more | 2017-03-21 |
| 9401309 | Multiheight contact via structures for a multilevel interconnect structure | Keisuke Izumi, Naohito Yanagida, Michiaki Sano, Takehiro Yamazaki, Akio Yanai +2 more | 2016-07-26 |
| 9362338 | Vertical thin film transistors in non-volatile storage systems | Naoki Takeguchi | 2016-06-07 |
| 9281314 | Non-volatile storage having oxide/nitride sidewall | Takashi Kashimura, Xiaolong Hu, Sayako Nagamine, Yusuke Yoshida, Akira Nakada +1 more | 2016-03-08 |
| 9236392 | Multiheight electrically conductive via contacts for a multilevel interconnect structure | Keisuke Izumi, Ryo Taura, Kentaro Sera, Akio Yanai | 2016-01-12 |
| 9123577 | Air gap isolation in non-volatile memory using sacrificial films | Hitomi Fujimoto, Ming Tian, Daisuke Maekawa | 2015-09-01 |
| 8937011 | Method of forming crack free gap fill | Hitomi Fujimoto, Chao Feng Yeh | 2015-01-20 |
| 8802561 | Method of inhibiting wire collapse | Chao Feng Yeh, Hitomi Fujimoto, Hisayuki Nozawa | 2014-08-12 |
| 7759722 | Semiconductor device and method of manufacturing the same | Tatsunori Murata, Koyu Asai | 2010-07-20 |