Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10313217 | System on chip (SoC) capable of sharing resources with network device and devices having the SoC | Jin Min Kim, Bo-Gyeong Kang, Myung-Koo Kang, Dae Hwan Kim | 2019-06-04 |
| 8051343 | Method of testing a memory module and hub of the memory module | Seung-Man Shin, Seung-Jin Seo, You-Keun Han | 2011-11-01 |
| 7930465 | Determining operation mode for semiconductor memory device | Seok-Il Kim, Young-man Ahn, Seung-Jin Seo | 2011-04-19 |
| 7868438 | Multi-chip package for reducing parasitic load of pin | Dong-Ho Lee, Hyun-Soon Jang | 2011-01-11 |
| 7849373 | Method of testing a memory module and hub of the memory module | Seung-Man Shin, Seung-Jin Seo, You-Keun Han | 2010-12-07 |
| 7847383 | Multi-chip package for reducing parasitic load of pin | Dong-Ho Lee | 2010-12-07 |
| 7818488 | Memory module with registers | Kwang Soo Park, Jeong-Hyeon Cho, Jung-Joon Lee, Young Yun, Kwang-Seop Kim | 2010-10-19 |
| 7656181 | Apparatus and method for testing circuit characteristics by using eye mask | Woo-Seop Kim, Jun Young Park, Sung-Je Hong, Sung-bum Cho, Hyun Chul KANG | 2010-02-02 |
| 7615869 | Memory module with stacked semiconductor devices | Chang-Woo Koo, Young-Jun Park | 2009-11-10 |
| 7606110 | Memory module, memory unit, and hub with non-periodic clock and methods of using the same | You-Keun Han, Hui-Chong Shin, Seung-Jin Seo, Young-man Ahn, Seung-Man Shin +2 more | 2009-10-20 |
| 7566958 | Multi-chip package for reducing parasitic load of pin | Dong-Ho Lee, Hyun-Soon Jang | 2009-07-28 |
| 7539910 | Memory module test system for memory module including hub | Young-man Ahn, Seung-Jin Seo, Seung-Man Shin | 2009-05-26 |
| 7505521 | Data transmission system and method | Jeong-Hyeon Cho, Jae-Jun Lee, Jong Hoon Kim | 2009-03-17 |
| 7447954 | Method of testing a memory module and hub of the memory module | Seung-Man Shin, Seung-Jin Seo, You-Keun Han | 2008-11-04 |
| 7350120 | Buffered memory module and method for testing same | Jeong-Hyeon Cho, Jae-Jun Lee | 2008-03-25 |
| 7334137 | Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller | Tae-Sung Jung, Myun-Joo Park | 2008-02-19 |
| 7313715 | Memory system having stub bus configuration | Chang-sik Yoo, Kye-hyun Kyung | 2007-12-25 |
| 7276786 | Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted | Jeong-Hyeon Cho, Jung-Joon Lee, Do Hyung Kim | 2007-10-02 |
| 7254675 | Memory system having memory modules with different memory device loads | Jae-Jun Lee, Myun-Joo Park | 2007-08-07 |
| 7227258 | Mounting structure in integrated circuit module | Jeong-Hyeon Cho, Jin-Kyu Chang | 2007-06-05 |
| 7219274 | Memory module and method of testing the same | Jung-Bae Lee, Hoe-Ju Chung | 2007-05-15 |
| 7215561 | Semiconductor memory system having multiple system data buses | Myun-Joo Park, Jae-Jun Lee | 2007-05-08 |
| 7180327 | Memory module system with efficient control of on-die termination | Jeong-Hyeon Cho, Jae-Jun Lee | 2007-02-20 |
| 7148563 | Multi-chip package for reducing parasitic load of pin | Dong-Ho Lee, Hyun-Soon Jang | 2006-12-12 |
| 7106613 | Memory module and a method of arranging a signal line of the same | Chil-Nam Yoon, Jung-Joon Lee, Jae-Jun Lee, Young-Jun Park, Il-Sung Yu | 2006-09-12 |