Issued Patents All Time
Showing 76–100 of 109 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8686500 | Double diffused metal oxide semiconductor device and manufacturing method thereof | Ching-Yao Yang | 2014-04-01 |
| 8653594 | Double diffused metal oxide semiconductor device and manufacturing method thereof | Ching-Yao Yang, Huan-Ping Chu, Hung-Der Su | 2014-02-18 |
| 8643136 | High voltage device and manufacturing method thereof | Kuo-Hsuan Lo | 2014-02-04 |
| 8592923 | Coupling well structure for improving HVMOS performance | Hsueh-Liang Chou, Chen-Bau Wu, Weng-Chu Chu, Fu-Jier Fan | 2013-11-26 |
| 8575693 | Double diffused metal oxide semiconductor device | Chien-Wei Chiu, Chien-Hao Huang | 2013-11-05 |
| 8524586 | Semiconductor overlapped PN structure and manufacturing method thereof | Chien-Hao Huang, Ying-Shiou Lin | 2013-09-03 |
| 8525258 | Method for controlling impurity density distribution in semiconductor device and semiconductor device made thereby | Ying-Shiou Lin | 2013-09-03 |
| 8501567 | Manufacturing method of high voltage device | Yuh-Chyuan Wang | 2013-08-06 |
| 8421150 | High voltage device and manufacturing method thereof | Huan-Ping Chu | 2013-04-16 |
| 8389341 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Puo-Yu Chiang, Ruey-Hsin Liu, Shun-Liang Hsu, Chyi-Chyuan Huang, Fu-Hsin Chen +1 more | 2013-03-05 |
| 8377787 | Alternating-doping profile for source/drain of a FET | Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen | 2013-02-19 |
| 8183626 | High-voltage MOS devices having gates extending into recesses of substrates | Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen | 2012-05-22 |
| 8178930 | Structure to improve MOS transistor on-breakdown voltage | Shen-Ping Wang, Wen-Liang Wang | 2012-05-15 |
| 8159029 | High voltage device having reduced on-state resistance | Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Chun Lin Tsai, Chien-Chih Chou | 2012-04-17 |
| 8158475 | Gate electrodes of HVMOS devices having non-uniform doping concentrations | Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Chun Lin Tsai, Chien-Chih Chou | 2012-04-17 |
| 8143130 | Method of manufacturing depletion MOS device | — | 2012-03-27 |
| 8129783 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Puo-Yu Chiang, Ruey-Hsin Liu, Shun-Liang Hsu | 2012-03-06 |
| 8114725 | Method of manufacturing MOS device having lightly doped drain structure | Ching-Yao Yang | 2012-02-14 |
| 8049295 | Coupling well structure for improving HVMOS performance | Hsueh-Liang Chou, Chen-Bau Wu, Weng-Chu Chu, Fu-Jier Fan | 2011-11-01 |
| 7989890 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Puo-Yu Chiang, Ruey-Hsin Liu, Shun-Liang Hsu, Chyi-Chyuan Huang, Fu-Hsin Chen +1 more | 2011-08-02 |
| 7977743 | Alternating-doping profile for source/drain of a FET | Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen | 2011-07-12 |
| 7960786 | Breakdown voltages of ultra-high voltage devices by forming tunnels | Eric Huang, Fu-Hsin Chen, Chyi-Chyuan Huang, Chung-Yeh Wu | 2011-06-14 |
| 7928508 | Disconnected DPW structures for improving on-state performance of MOS devices | Chih-Wen Yao, Puo-Yu Chiang, Tsai Chun Lin | 2011-04-19 |
| 7888216 | Method of fabricating a high performance power MOS | Yu-Wen Chen, Fu-Hsin Chen, Yt Tsai | 2011-02-15 |
| 7888734 | High-voltage MOS devices having gates extending into recesses of substrates | Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen | 2011-02-15 |