Issued Patents All Time
Showing 126–150 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9036065 | Shared-counter image sensor | — | 2015-05-19 |
| 9037949 | Error correction in a memory device | Suresh Rajan, Ian Shaeffer, Frederick A. Ware, Wayne F. Ellis | 2015-05-19 |
| 9001251 | Oversampled image sensor with conditional pixel readout | Craig M. Smith, Michael Guidash, Jay Endsley, James E. Harris | 2015-04-07 |
| 9001606 | Memory methods and systems with adiabatic switching | Brent Haukness | 2015-04-07 |
| 8982598 | Stacked memory device with redundant resources to correct defects | Paul D. Franzon, Evan Lawrence Erickson, Frederick A. Ware | 2015-03-17 |
| 8930779 | Bit-replacement technique for DRAM error correction | Frederick A. Ware, Ely Tsern | 2015-01-06 |
| 8918702 | Semiconductor memory having non-standard form factor | — | 2014-12-23 |
| 8908454 | Memory architecture with redundant resources | Brent Haukness | 2014-12-09 |
| 8885423 | DRAM sense amplifier that supports low memory-cell capacitance | Gary B. Bronner | 2014-11-11 |
| 8811095 | Methods and circuits for dynamically scaling DRAM power and performance | Ely Tsern, Craig E. Hampel, Scott C. Best | 2014-08-19 |
| 8717797 | Semiconductor memory device with hierarchical bitlines | — | 2014-05-06 |
| 8473808 | Semiconductor memory having non-standard form factor | — | 2013-06-25 |
| 7956644 | Peak power reduction using fixed bit inversion | — | 2011-06-07 |
| 7937631 | Method for self-test and self-repair in a multi-chip package environment | — | 2011-05-03 |
| 7797511 | Memory refresh system and method | — | 2010-09-14 |
| 7440347 | Circuit and method to find wordline-bitline shorts in a DRAM | — | 2008-10-21 |
| 7375999 | Low equalized sense-amp for twin cell DRAMs | — | 2008-05-20 |
| 7342291 | Standby current reduction over a process window with a trimmable well bias | — | 2008-03-11 |
| 7333383 | Fuse resistance read-out circuit | — | 2008-02-19 |
| 7293190 | Noisy clock test method and apparatus | — | 2007-11-06 |
| 7254089 | Memory with selectable single cell or twin cell configuration | Harald Lorenz, Wolfgang Hokenmaier | 2007-08-07 |
| 7227799 | Sense amplifier for eliminating leakage current due to bit line shorts | — | 2007-06-05 |
| 7060529 | Multiple chip semiconductor arrangement having electrical components in separating regions | Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller +2 more | 2006-06-13 |
| 7060566 | Standby current reduction over a process window with a trimmable well bias | — | 2006-06-13 |
| 6815803 | Multiple chip semiconductor arrangement having electrical components in separating regions | Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller +2 more | 2004-11-09 |