Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7330952 | Integrated circuit memory device having delayed write timing based on read response time | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Abhijit M. Abhyankar +2 more | 2008-02-12 |
| 7288973 | Method and apparatus for fail-safe resynchronization with minimum latency | Jared L. Zerbe, Michael Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan +1 more | 2007-10-30 |
| 7287119 | Integrated circuit memory device with delayed write command processing | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Abhijit M. Abhyankar +2 more | 2007-10-23 |
| 7197611 | Integrated circuit memory device having write latency function | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Abhijit M. Abhyankar +2 more | 2007-03-27 |
| 7149856 | Method and apparatus for adjusting the performance of a synchronous memory system | Bruno W. Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark +3 more | 2006-12-12 |
| 7142475 | Memory device having a configurable oscillator for refresh operation | Ely Tsern, Richard M. Barth, Craig E. Hampel | 2006-11-28 |
| 7047375 | Memory system and method for two step memory write operations | Frederick A. Ware, Craig E. Hampel | 2006-05-16 |
| 6949958 | Phase comparator capable of tolerating a non-50% duty-cycle clocks | Jared L. Zerbe, Michael Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan +1 more | 2005-09-27 |
| 6889300 | Memory system and method for two step write operations | Frederick A. Ware, Craig E. Hampel | 2005-05-03 |
| 6868474 | High performance cost optimized memory | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Abhijit M. Abhyankar +2 more | 2005-03-15 |
| 6842864 | Method and apparatus for configuring access times of memory devices | Richard M. Barth, Ely Tsern, Craig E. Hampel, Frederick A. Ware, Todd Bystrom +1 more | 2005-01-11 |
| 6778458 | Dram core refresh with reduced spike current | Ely Tsern, Richard M. Barth, Craig E. Hampel | 2004-08-17 |
| 6757789 | Apparatus and method for maximizing information transfers over limited interconnect resources | Abhijit M. Abhyankar, Frederick A. Ware, Donald C. Stark, Craig E. Hampel | 2004-06-29 |
| 6597616 | DRAM core refresh with reduced spike current | Ely Tsern, Richard M. Barth, Craig E. Hampel | 2003-07-22 |
| 6553452 | Synchronous memory device having a temperature register | Bruno W. Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark +3 more | 2003-04-22 |
| 6513103 | Method and apparatus for adjusting the performance of a synchronous memory system | Bruno W. Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark +3 more | 2003-01-28 |
| 6473439 | Method and apparatus for fail-safe resynchronization with minimum latency | Jared L. Zerbe, Michael Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan +1 more | 2002-10-29 |
| 6401167 | High performance cost optimized memory | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Abhijit M. Abhyankar +2 more | 2002-06-04 |
| 6378018 | Memory device and system including a low power interface | Ely Tsern, Thomas J. Holman, Richard M. Barth, Andrew V. Anderson, Craig E. Hampel +2 more | 2002-04-23 |
| 6347354 | Apparatus and method for maximizing information transfers over limited interconnect resources | Abhijit M. Abhyankar, Frederick A. Ware, Donald C. Stark, Craig E. Hampel | 2002-02-12 |
| 6345009 | Apparatus and method for refreshing subsets of memory devices in a memory system | Ely Tsern, Richard M. Barth, Craig E. Hampel, Thomas J. Holman, Andrew V. Anderson | 2002-02-05 |
| 6343042 | DRAM core refresh with reduced spike current | Ely Tsern, Richard M. Barth, Craig E. Hampel | 2002-01-29 |
| 6343352 | Method and apparatus for two step memory write operations | Frederick A. Ware, Craig E. Hampel | 2002-01-29 |
| 6310814 | Rambus DRAM (RDRAM) apparatus and method for performing refresh operations | Craig E. Hampel, Richard M. Barth, Bradley A. May, Ramprasad Satagopan, Frederick A. Ware | 2001-10-30 |
| 6266292 | DRAM core refresh with reduced spike current | Ely Tsern, Richard M. Barth, Craig E. Hampel | 2001-07-24 |