Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6859872 | Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation | John H. Edmondson, Jose Fridman, Marc Hoffman | 2005-02-22 |
| 6763453 | Security on hardware loops | Ravi P. Singh, Thomas Tomazin, Charles P. Roth | 2004-07-13 |
| 6526562 | Methods for developing an integrated circuit chip design | Elie I. Haddad, James Monaco, Thomas Tomazin | 2003-02-25 |
| 6446181 | System having a configurable cache/SRAM memory | Hebbalalu S. Ramagopal, David B. Witt, Michael S. Allen, Moinul Syed, Ravi Kolagotla +1 more | 2002-09-03 |
| 6088782 | Method and apparatus for moving data in a parallel processor using source and destination vector registers | De-Lei Lee, L. Rodney Goke | 2000-07-11 |
| 6044392 | Method and apparatus for performing rounding in a data processor | Thomas Tomazin | 2000-03-28 |
| 5727229 | Method and apparatus for moving data in a parallel processor | Larry Kan, Chuan-Chang Hung, Meltin Bell | 1998-03-10 |
| 5619711 | Method and data processing system for arbitrary precision on numbers | — | 1997-04-08 |
| 5276635 | Method and apparatus for performing carry look-ahead addition in a data processor | Ajay Naini | 1994-01-04 |
| 5268995 | Method for executing graphics Z-compare and pixel merge instructions in a data processor | Keith E. Diefendorff | 1993-12-07 |
| 5265043 | Wallace tree multiplier array having an improved layout topology | Ajay Naini, Lisa J. Craft | 1993-11-23 |
| 5220525 | Recoded iterative multiplier | Ajay Naini | 1993-06-15 |