Issued Patents All Time
Showing 51–75 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9154140 | Delay locked loop | Dong-Hoon Jung, Jin-Hyuk Kim, Kyung-Ho Ryu, Byoung-Chan Oh | 2015-10-06 |
| 9111623 | NMOS-offset canceling current-latched sense amplifier | Taehui Na, Ji Su Kim, Jung Pill Kim, Seung H. Kang | 2015-08-18 |
| 9111635 | Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods | Younghwi Yang, Bin Yang, Zhongze Wang, Choh Fei Yeap | 2015-08-18 |
| 9035684 | Delay locked loop and method of generating clock | Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park | 2015-05-19 |
| 8864376 | Temperature sensing circuit | Kwang-seok Kim, Seung-Han Woo, Kyung-Ho Ryu, Dong-Hoon Jung | 2014-10-21 |
| 8717811 | Latching circuit | Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang | 2014-05-06 |
| 8693272 | Sensing circuit | Jisu Kim, Kyungho Ryu, Seung H. Kang | 2014-04-08 |
| 8686772 | Frequency multiplier and method of multiplying frequency | Jiwan Jung, Kyungho Ryu | 2014-04-01 |
| 8670266 | Non-volatile flip-flop | Kyungho Ryu, Youngdon Jung, Jisu Kim, Jung Pill Kim, Seung H. Kang | 2014-03-11 |
| 8611132 | Self-body biasing sensing circuit for resistance-based memories | Jisu Kim, Youngdon Jung, Jung Pill Kim, Seung H. Kang | 2013-12-17 |
| 8531902 | Sensing circuit | Jisu Kim, Kyungho Ryu, Jung Pill Kim, Seung H. Kang | 2013-09-10 |
| 8519758 | Digital DLL including skewed gate type duty correction circuit and duty correction method thereof | Won Gi Lee, Donghwan Lee, Heechai Kang, Kyungho Ryu, Donghoon Jung | 2013-08-27 |
| 8493116 | Clock delay circuit and delay locked loop including the same | Jong-Ryun Choi, Suho Kim, Heechai Kang, Kyungho Ryu | 2013-07-23 |
| 8447547 | Static noise margin estimation | Seung-Chul Song, Hyunkook Park | 2013-05-21 |
| 8432727 | Invalid write prevention for STT-MRAM array | Kyungho Ryu, Jisu Kim, Seung H. Kang | 2013-04-30 |
| 8423329 | System and method of adjusting a resistance-based memory circuit parameter | Jisu Kim, Jee-Hwan Song, Seung H. Kang | 2013-04-16 |
| 8406064 | Latching circuit | Kyungho Ryu, Jisu Kim, Jung Pill Kim, Seung H. Kang | 2013-03-26 |
| 8335101 | Resistance-based memory with reduced voltage input/output device | Jisu Kim, Seung H. Kang | 2012-12-18 |
| 8161430 | System and method of resistance based memory circuit parameter adjustment | Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon | 2012-04-17 |
| 8154903 | Split path sensing circuit | Jisu Kim, Seung H. Kang | 2012-04-10 |
| 8144509 | Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size | Mehdi Hamidi Sani, Seung H. Kang, Sei Seung Yoon | 2012-03-27 |
| 8049543 | Delay locked loop, electronic device including the same, and method of operating the same | Hee Chai Kang, Kyeong Ho Ryu, Won Gi Lee, Dong Hwan Lee, Alex Joo +1 more | 2011-11-01 |
| 7979832 | Process variation tolerant memory design | Sei Seung Yoon, Hyunwoo Nho | 2011-07-12 |
| 7889585 | Balancing a signal margin of a resistance based memory circuit | Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon, Mehdi Hamidi Sani | 2011-02-15 |
| 7872930 | Testing a memory device having field effect transistors subject to threshold voltage shifts caused by bias temperature instability | Nan Chen, Sian-Yee Sean Lee, Zhongze Wang | 2011-01-18 |