Issued Patents All Time
Showing 76–100 of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9818170 | Processing unaligned block transfer operations | — | 2017-11-14 |
| 9804995 | Computational resource pipelining in general purpose graphics processing unit | Alexei V. Bourd, Aleksandra L. Krstic, Robert J. Simpson, Colin Christopher Sharp, Chun Yu | 2017-10-31 |
| 9799094 | Per-instance preamble for graphics processing | Lin Chen, Richard Hammerstone, Jiaji Liu, Chihong Zhang, Yun Du | 2017-10-24 |
| 9799089 | Per-shader preamble for graphics processing | Lin Chen, Yun Du, Guofang Jiao, Chun Yu, David Rigel Garcia Garcia | 2017-10-24 |
| 9747104 | Utilizing pipeline registers as intermediate storage | Lin Chen, Yun Du, Sumesh Udayakumaran, Chihong Zhang | 2017-08-29 |
| 9697580 | Dynamic pipeline for graphics processing | Liang Li, Guofang Jiao, Zhenyu Qi, Gregory Pitarys, Scott William Nolan | 2017-07-04 |
| 9665370 | Skipping of data storage | Yun Du, Lin Chen, Chihong Zhang, Chun Yu | 2017-05-30 |
| 9645792 | Emulation of fused multiply-add operations | Pramod Vasant Argade, Chiente Ho, Stewart Griffin Hall, Lin Chen | 2017-05-09 |
| 9633411 | Load scheme for shared register in GPU | Yun Du, Lin Chen, Guofang Jiao, Chun Yu | 2017-04-25 |
| 9582846 | Graphics processing architecture employing a unified shader | Stephen L. Morein, Laurent Lefebvre, Andi Skende | 2017-02-28 |
| 9569811 | Rendering graphics to overlapping bins | Tao Wang, Chunhui Mei, Gang Zhong, Feng Ge | 2017-02-14 |
| 9489313 | Conditional page fault control for page residency | David A. Gotwalt, Thomas Edwin Frisinger, Eric Demers, Colin Christopher Sharp | 2016-11-08 |
| 9483861 | Tile-based rendering | Christopher Paul Frascati, Avinash Seetharamaiah | 2016-11-01 |
| 9442780 | Synchronization of shader operation | — | 2016-09-13 |
| 9412197 | Patched shading in graphics processing | Vineet Goel, Donghyun Kim | 2016-08-09 |
| 9311743 | Selectively merging partially-covered tiles to perform hierarchical z-culling | Tao Wang, Shambhoo Khandelwal | 2016-04-12 |
| 9299123 | Indexed streamout buffers for graphics processing | Vineet Goel | 2016-03-29 |
| 9256429 | Selectively activating a resume check operation in a multi-threaded processing system | Lin Chen, Yun Du | 2016-02-09 |
| 9245496 | Multi-mode memory access techniques for performing graphics processing unit-based memory transfer operations | Tao Wang, Shambhoo Khandelwal | 2016-01-26 |
| 9230518 | Fault-tolerant preemption mechanism at arbitrary control points for graphics processing | Christopher Paul Frascati, Murat Balci, Avinash Seetharamaiah, Alexei V. Bourd | 2016-01-05 |
| 9218289 | Multi-core compute cache coherency with a release consistency memory ordering model | Bohuslav Rychlik, Tzung Ren Tzeng, Alexei V. Bourd, Colin Christopher Sharp, Eric Demers | 2015-12-22 |
| 9087409 | Techniques for reducing memory access bandwidth in a graphics processing system based on destination alpha values | — | 2015-07-21 |
| 9087410 | Rendering graphics data using visibility information | Avinash Seetharamaiah, Murat Balci, Christopher Paul Frascati | 2015-07-21 |
| 9071787 | Display information feedback | Edward G. Callway, David Glen, Gaurav Arora, Philip L. Swan | 2015-06-30 |
| 8931108 | Hardware enforced content protection for graphics processing units | Colin Christopher Sharp, Sudeep Ravi Kottilingal, Thomas Edwin Frisinger | 2015-01-06 |