Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies

Test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies

US Patent 9691669 · Granted Jun 27, 2017

Estimated economic value: $2,044,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Embedded system to characterize BTI degradation effects in MOSFETs2025
Test structures for measuring silicon thickness in fully depleted silicon-on-ins2020
Test structures for measuring silicon thickness in fully depleted silicon-on-ins2020
Test structures for measuring silicon thickness in fully depleted silicon-on-ins2020
Test structures for measuring silicon thickness in fully depleted silicon-on-ins2020
Method for applying charge-based-capacitance-measurement with switches using onl2020
Passive array test structure for cross-point memory characterization2020
Passive array test structure for cross-point memory characterization2020
Test structures and method for electrical measurement of FinFET fin height2020
Test structures and method for electrical measurement of FinFET fin height2020
Method for accurate measurement of leaky capacitors using charge based capacitan2018
Method for accurate measurement of leaky capacitors using charge based capacitan2018