Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies

Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies

US Patent 10852337 · Granted Dec 1, 2020

Estimated economic value: $4,373,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Embedded system to characterize BTI degradation effects in MOSFETs2025
Embedded system to characterize BTI degradation effects in MOSFETs2025
IC with test structures and e-beam pads embedded within a contiguous standard ce2021
IC with test structures and e-beam pads embedded within a contiguous standard ce2021
IC with test structures and e-beam pads embedded within a contiguous standard ce2021
IC with test structures and E-beam pads embedded within a contiguous standard ce2021
IC with test structures and e-beam pads embedded within a contiguous standard ce2021
IC with test structures and E-beam pads embedded within a contiguous standard ce2021
Method for processing a semiconductor wafer using non-contact electrical measure2020
IC with test structures embedded within a contiguous standard cell area2020
Method and apparatus for direct testing and characterization of a three dimensio2020
Method for applying charge-based-capacitance-measurement with switches using onl2020