Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection

Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection

US Patent 9589876 · Granted Mar 7, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor device and method of forming an optical semiconductor package with2025
Side-solderable leadless package2025
Reliable semiconductor packages2025
Semiconductor device and method of forming substrate with 3-sided wettable flank2024
Reliable semiconductor packages2024
Reliable semiconductor packages2024
Semiconductor package with dams2024
Side-solderable leadless package2023
Reliable semiconductor packages for sensor chips2023
Semiconductor device and method of forming mold degating structure for pre-molde2022
Semiconductor device and method of forming mold degating structure for pre-molde2022
Side-solderable leadless package2021