Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

US Patent 9577100 · Granted Feb 21, 2017

Estimated economic value: $8,671,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electronically programmable fuse with heating transistors2025
Lateral phototransistor2025
Semiconductor-on-insulator field-effect transistors including stress-inducing co2025
Semiconductor device2025
In-situ low temperature dielectric deposition and selective trim of phase change2025
Vertically stacked FET with strained channel2025
Nanowire source/drain formation for nanosheet device2025
Strain generation and anchoring in gate-all-around field effect transistors2025
IC device with vertically-graded silicon germanium region adjacent device channe2025
Buried power rail with robust connection to a wrap around contact2025
Semiconductor structure with wrapped-around backside contact2025
Two-dimensional vertical fins2025