Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method to speed up PLL lock time on subsequent calibrations via stored band values

System and method to speed up PLL lock time on subsequent calibrations via stored band values

US Patent 9571111 · Granted Feb 14, 2017

Estimated economic value: $13,147,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic sequential approximation register (SAR) analog-to-digital converter (ADC2020
Self-moderating bus arbitration architecture2019
Managing data flow in VCSEL-based optical communications system2019
Linear feedback shift register-based clock signal generator, time domain-interle2019
Temperature compensation for reference voltages in an analog-to-digital converte2019
Self-moderating bus arbitration architecture2019
Control of VCSEL-based optical communications system2019
Peaking amplifier frequency tuning2019
Phase rotator apparatus2018
Peaking amplifier frequency tuning2018
Peaking amplifier frequency tuning2018
Area and/or power optimization through post-layout modification of integrated ci2017