Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Combined rank and linear address incrementing utility for computer memory test operations

Combined rank and linear address incrementing utility for computer memory test operations

US Patent 9298614 · Granted Mar 29, 2016

Estimated economic value: $2,226,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic multi-lane degrade capability to facilitate uninterrupted service2025
Error protection analysis of an integrated circuit2025
Cable pair concurrent servicing2024
Low-latency deserializer having fine granularity and defective-lane compensation2024
Host synchronized autonomous data chip address sequencer for a distributed buffe2023
Low-latency, high-availability and high-speed SerDes interface having multiple s2023
Low latency availability in degraded redundant array of independent memory2023
Address/command chip controlled data chip address sequencing for a distributed m2023
Refresh-hiding memory system staggered refresh2022
Address/command chip synchronized autonomous data chip address sequencer for a d2022
Low latency availability in degraded redundant array of independent memory2021
Use of a cyclic redundancy code multiple-input shift register to provide early w2021