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Home › Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process

Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process

US Patent 9171754 · Granted Oct 27, 2015

Estimated economic value: $712,000 ⓘ

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