Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

US Patent 8936977 · Granted Jan 20, 2015

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Deep trench isolation structures with a substrate connection2024
Laterally-diffused metal-oxide-semiconductor devices with a multiple-thickness b2024
Device including a floating gate electrode and a layer of ferroelectric material2022
Buried-channel low noise transistors and methods of making such devices2020
Transistor element with reduced lateral electrical field2020
High voltage Schottky diode and manufacturing method thereof2020
Low on resistance high voltage metal oxide semiconductor transistor2019
Contact structures to deep trench isolation structures and method of nanufacturi2019
Three-dimensional transistor with improved channel mobility2019
Three-dimensional transistor with improved channel mobility2019
Communicating optical signals between stacked dies2019
Methods for forming integrated circuits that include a dummy gate structure2018