Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor device with stressed fin sections

Semiconductor device with stressed fin sections

US Patent 8912603 · Granted Dec 16, 2014

Estimated economic value: $1,928,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor device with doped region adjacent isolation structure in extension2021
Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs2019
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned a2019
Simplified gate to source/drain region connections2019
Method, apparatus, and system for using a cover mask for enabling metal line jum2018
Method, apparatus, and system for using a cover mask for enabling metal line jum2018
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned a2018
Pass-through contact using silicide2017
Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs2017
CMOS circuit having a tensile stress layer overlying an NMOS transistor and over2016
Methods for converting planar designs to FinFET designs in the design and fabric2016
Semiconductor structures and methods for forming isolation between Fin structure2016