Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Clock alias for timing analysis of an integrated circuit design

Clock alias for timing analysis of an integrated circuit design

US Patent 8438514 · Granted May 7, 2013

Estimated economic value: $10,737,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Implementing enhanced physical design quality using historical placement analyti2015
Implementing enhanced physical design quality using historical placement analyti2015
Specifying circuit level connectivity during circuit design synthesis2014
Clock alias for timing analysis of an integrated circuit design2014
Clock alias for timing analysis of an integrated circuit design2014
Clock alias for timing analysis of an integrated circuit design2013
Efficiently applying a single timing assertion to multiple timing points in a ci2013
Efficiently applying a single timing assertion to multiple timing points in a ci2013
Implementing timing pessimism reduction for parallel clock trees2012
Implementing spare latch placement quality determination2012
Implementing spare latch placement quality determination2012
Implementing forward tracing to reduce pessimism in static timing of logic block2012