Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip

Implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip

US Patent 8271923 · Granted Sep 18, 2012

Estimated economic value: $5,189,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Determining positions of storage elements in a logic design2018
Implementing enhanced physical design quality using historical placement analyti2015
Implementing enhanced physical design quality using historical placement analyti2015
Implementing enhanced net routing congestion resolution of non-rectangular or re2015
Analyzing sparse wiring areas of an integrated circuit design2015
Implementing Z directional macro port assignment2014
Analyzing timing requirements of a hierarchical integrated circuit design2014
Changing the location of a buffer bay in a netlist2014
Clock alias for timing analysis of an integrated circuit design2014
Swapping ports to change the timing window overlap of adjacent nets2014
Clock alias for timing analysis of an integrated circuit design2013
Slack-based timing budget apportionment2013