Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors

Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors

US Patent 7586153 · Granted Sep 8, 2009

Estimated economic value: $20,470,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dual metal gate structures on nanoribbon semiconductor devices2025
Source/drain regions in integrated circuit structures2025
Integrated circuit structures with gate cuts above buried power rails2025
Gate spacing in integrated circuit structures2025
Self-aligned lateral contacts2025
Transistor arrangements with stacked trench contacts and gate straps2025
Stacked vias with bottom portions formed using selective growth2025
Device contact sizing in integrated circuit structures2025
Contact over active gate structures with tapered gate or trench contact for adva2025
Use of a placeholder for backside contact formation for transistor arrangements2024
Buried power rails with self-aligned vias to trench contacts2024
Device contacts in integrated circuit structures2024