Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions

Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions

US Patent 7214992 · Granted May 8, 2007

Estimated economic value: $12,715,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Contact array optimization for ESD devices2018
Method and apparatus for reducing plasma process induced damage in integrated ci2013
Method for designing and manufacturing a PMOS device with drain junction breakdo2011
System and method for providing a poly cap and a no field oxide area to prevent 2011
Electrical test structure and method for characterization of deep trench sidewal2011
System and method for increasing breakdown voltage of LOCOS isolated devices2011
Method of monitoring process misalignment to reduce asymmetric device operation 2010
Method of controlling the breakdown voltage of BSCRs and BJT clamps2010
MOS transistor and method of forming the MOS transistor with a SiON etch stop la2010
Method for designing and manufacturing a PMOS device with drain junction breakdo2009
Method of forming a silicide bridged anti-fuse with a tungsten plug metalization2009
System and method for providing a poly cap and a no field oxide area to prevent 2009