Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for providing debug functionality in a buffered memory channel

Method and apparatus for providing debug functionality in a buffered memory channel

US Patent 6996749 · Granted Feb 7, 2006

Estimated economic value: $20,276,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Page offlining based on fault-aware prediction of imminent memory error2025
Perfect row hammer tracking with multiple count increments2025
Per bank refresh hazard avoidance for large scale memory2025
Adaptive internal error scrubbing and error handling2025
Method and apparatus for memory chip row hammer threat backpressure signal and h2025
Logic die in a multi-chip package having a configurable physical interface to on2025
Stacked memory chip solution with reduced package inputs/outputs (I/Os)2025
Double fetch for long burst length memory data transfer2025
Per channel thermal management techniques for stacked memory2025
Uncorrectable memory error prediction2025
Adaptive error correction to improve system memory reliability, availability, an2025
Dynamic random access memory (DRAM) with scalable meta data2025