Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of forming low resistance metal silicide region on a gate electrode of a transistor

Method of forming low resistance metal silicide region on a gate electrode of a transistor

US Patent 6423634 · Granted Jul 23, 2002

Estimated economic value: $1,368,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for maintaining wood railroad ties2022
Composition, device, and method for maintaining wood railroad ties2022
Methods of reducing material loss in isolation structures by introducing inert a2014
Semiconductor device comprising replacement gate electrode structures and self-a2014
Temperature monitoring in a semiconductor device by using a PN junction based on2014
High-k metal gate electrode structure formed by removing a work function on side2014
Semiconductor device comprising a metal gate stack of reduced height and method 2012
Enhancing transistor characteristics by a late deep implantation in combination 2012
Drive current adjustment for transistors by local gate engineering2012
In situ monitoring of metal contamination during microstructure processing2012
Reducing the creation of charge traps at gate dielectrics in MOS transistors by 2012
Etch stop layer of reduced thickness for patterning a dielectric material in a c2012