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Home › Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space

Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space

US Patent 5661069 · Granted Aug 26, 1997

Estimated economic value: $18,348,000 ⓘ

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