Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Single event upset in SRAM cells in FPGAs with high resistivity gate structures

Single event upset in SRAM cells in FPGAs with high resistivity gate structures

US Patent 7452765 · Granted Nov 18, 2008

Estimated economic value: $2,887,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Rayleigh-Raman polychromatic laser guide star2025
Achromatic and polarization adaptive optics system2025
Forming and/or configuring stacked dies2024
Compute dataflow architecture2023
Designing single event upset latches2023
Distributed watchdog timer and active token exchange2023
Anti-spoofing of neural networks2022
Compute dataflow architecture2022
On-die virtual probes (ODVP) for integrated circuitries2022
Power delivery network for active-on-active stacked integrated circuits2022
Power delivery network for active-on-active stacked integrated circuits2022
Multi-chip stacked devices2022