Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for interconnect testing without speed degradation

Method and apparatus for interconnect testing without speed degradation

US Patent 5513186 · Granted Apr 30, 1996

Estimated economic value: $28,512,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Processor core communication in multi-core processor2013
Method for ensuring mutual exclusivity of selected signals during application of2000
Clock stopping schemes for data buffer1999
Mutual exclusivity circuit for use in test pattern application scan architecture1999
Boundary-scan circuit for use with linearized impedance control type output driv1999
Method for interfacing boundary-scan circuitry with linearized impedance control1999
Method and apparatus for on die testing1999
Control circuit for deterministic stopping of an integrated circuit internal clo1999
Final stage clock buffer in a clock distribution network1998
Integrated circuit with identification signal writing circuitry distributed on m1998
Pipelined scan enable for fast scan testing1998
Method and apparatus for identifying faults within a system1996