Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for preventing the erasure and programming of a nonvolatile memory

Method and apparatus for preventing the erasure and programming of a nonvolatile memory

US Patent 4975883 · Granted Dec 4, 1990

Estimated economic value: $9,136,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Apparatuses and methods for concurrently accessing multiple partitions of a non-2023
Resistance reduction for word lines in memory arrays2023
Apparatuses and methods for concurrently accessing multiple partitions of a non-2022
Memory arrays with bonded and shared logic circuitry2021
Apparatuses and methods for concurrently accessing multiple partitions of a non-2020
Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer2020
Wordline bridge in a 3D memory array2019
Method and apparatus for reducing stress across capacitors used in integrated ci2010
Dividing a flash memory operation into phases2008
Method and apparatus for matched-reference sensing architecture for non-volatile2004
Method and apparatus for matched-reference sensing architecture for non-volatile2003
Voltage driver for a memory2002