Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertion

Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertion

US Patent 12340099 · Granted Jun 24, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Enhanced accuracy of bit line reading for an in-memory compute operation by acco2025
Bit line read current mirroring circuit for an in-memory compute operation where2025
At-speed transition fault testing for a multi-port and multi-clock memory2025
In-memory computation circuit using static random access memory (SRAM) array seg2025
Memory architecture supporting both conventional memory access mode and digital 2025
Tuning of read/write cycle time delay for a memory circuit dependent on operatio2025
Adaptive word line underdrive control for an in-memory compute operation where s2025
Selective bit line clamping control for an in-memory compute operation where sim2025
Modular memory architecture with more significant bit sub-array word line activa2025
Bit-cell architecture based in-memory compute2024
Adaptive body bias management for an in-memory compute operation where simultane2024
Built-in self test circuit for segmented static random access memory (SRAM) arra2024