Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Modular memory architecture with more significant bit sub-array word line activation in single-cycle read-modify-write operation dependent on less significant bit sub-array data content

Modular memory architecture with more significant bit sub-array word line activation in single-cycle read-modify-write operation dependent on less significant bit sub-array data content

US Patent 12210754 · Granted Jan 28, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Static random access memory supporting a single clock cycle read-modify-write op2025
SRAM with fast, controlled peak current, power efficient array reset, and data c2024
Low power and fast memory reset2024
Modular memory architecture with gated sub-array operation dependent on stored d2024
Static random access memory supporting a single clock cycle read-modify-write op2024
Self-adjustable self-timed dual-rail SRAM2023
Parallel port enablement in pseudo-dual-port memory designs2022
Temperature compensated read assist circuit for a static random access memory (S2018
Tire tread2017