{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown", "item": "https://www.patentleaderboard.com/patent/11757027"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025

E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown

US Patent 11757027 · Granted Sep 12, 2023

Estimated economic value: $19,004,000

Assignee

Inventors

View full patent text on Google Patents →