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Home › Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

US Patent 10546836 · Granted Jan 28, 2020

Estimated economic value: $1,679,000 ⓘ

Assignee

IBM

Inventors

Bing Dang (140 patents)
Li-Wen Hung (65 patents)
John U. Knickerbocker (308 patents)
Jae-Woong Nah (138 patents)

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