Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods

US Patent 10170389 · Granted Jan 1, 2019

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Microelectronic devices including stair step structures, and related memory devi2025
Memory circuitry and method used in forming memory circuitry2025
Methods of forming microelectronic devices including differently sized conductiv2025
Memory device including support structures and contact structures having differe2025
Repair techniques for coupled memory dies2025
Shape processes, feedstock materials, conductive materials and/or assemblies2025
Protected regions management of memory2025
High speed shear-assisted extrusion2025
Apparatuses including interconnect structures including dielectric material surr2025
Devices and methods for performing shear-assisted extrusion and extrusion proces2025
Microelectronic devices with vertically recessed channel structures and discrete2025
Memory module multiple port buffer techniques2025