Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors

Integrated circuit with multi-level arrangement of e-fuse protected decoupling capacitors

US Patent 10014252 · Granted Jul 3, 2018

Estimated economic value: $5,535,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Etch profile control of via opening2025
Bridge die having different surface orientation than IC dies interconnected by t2025
Antenna apparatus2025
Methods and systems for improving surface mount joinder2025
Interposer including stepped surfaces and methods of forming the same2025
Semiconductor package with ball grid array connection having improved reliabilit2025
Integrated circuit package and method of forming same2025
Semiconductor device including cumulative sealing structures2025
Method for forming a semiconductor device including forming a first interconnect2025
Semiconductor devices and methods of manufacture2025
P-GaN high-electron-mobility transistor2025
Forming large chips through stitching2024