Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7411409 | Digital leakage detector that detects transistor leakage current in an integrated circuit | Andrew J. Demas, Greg M. Hess, Ashish R. Jain | 2008-08-12 |
| 7373569 | Pulsed flop with scan circuitry | — | 2008-05-13 |
| 7319344 | Pulsed flop with embedded logic | — | 2008-01-15 |
| 7245150 | Combined multiplex or/flop | Rajat Goel, Andrew J. Demas, Shih-Chieh Wen, Honkai Tam | 2007-07-17 |
| 7088144 | Conditional precharge design in staticized dynamic flip-flop with clock enable | Bo Tang, Geoffrey Pilling | 2006-08-08 |
| 6911854 | Clock skew tolerant clocking scheme | — | 2005-06-28 |
| 6828852 | Active pulsed scheme for driving long interconnects | Andrew J. Demas | 2004-12-07 |
| 6768345 | Method for clock control of clocked full-rail differential logic circuits with sense amplifier and shut-off | Swee Yew Choe | 2004-07-27 |
| 6765415 | Clocked full-rail differential logic with shut-off | Swee Yew Choe | 2004-07-20 |
| 6741113 | Modified high speed flop design with self adjusting, data selective, evaluation window | Bo Tang | 2004-05-25 |
| 6737889 | Method for increasing the power efficiency and noise immunity of clocked full-rail differential logic | Swee Yew Choe | 2004-05-18 |
| 6703867 | Clocked full-rail differential logic with sense amplifier and shut-off | Swee Yew Choe | 2004-03-09 |
| 6624664 | Clocked full-rail differential logic with sense amplifiers | Swee Yew Choe | 2003-09-23 |
| 6614264 | Method for increasing the load capacity of full-rail differential logic | Swee Yew Choe | 2003-09-02 |
| 6536022 | Two pole coupling noise analysis model for submicron integrated circuit design verification | Kathirgamar Aingaran, Chaim Amir, Chin Kim | 2003-03-18 |
| 6353339 | Modified domino logic circuit with high input noise rejection | — | 2002-03-05 |
| 6222404 | Edge-triggered dual-rail dynamic flip-flop with an enhanced self-shut-off mechanism | Anup S. Mehta, Chaim Amir, Ashutosh Kumar Das | 2001-04-24 |
| 6121807 | Single phase edge-triggered dual-rail dynamic flip-flop | Chaim Amir | 2000-09-19 |
| 6043696 | Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop | Chaim Amir | 2000-03-28 |
| 6023179 | Method of implementing a scan flip-flop using an edge-triggered staticized dynamic flip-flop | — | 2000-02-08 |
| 6018254 | Non-blocking delayed clocking system for domino logic | Alan C. Rogers, Chaim Amir, Jason M. Hart | 2000-01-25 |
| 5983013 | Method for generating non-blocking delayed clocking signals for domino logic | Alan C. Rogers, Chaim Amir, Jason M. Hart | 1999-11-09 |
| 5933038 | Flip-flop with logic function incorporated therein with minimal time penalty | — | 1999-08-03 |
| 5920218 | Single-phase edge-triggered dual-rail dynamic flip-flop | Chaim Amir | 1999-07-06 |
| 5917355 | Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism | — | 1999-06-29 |