Issued Patents All Time
Showing 51–75 of 125 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6879929 | Sense amplifier thermal correction scheme | Shaishav Desai, Raymond A. Heald | 2005-04-12 |
| 6873503 | SSTL pull-up pre-driver design using regulated power supply | Brian Amick, Lynn Warriner, Tri Tran | 2005-03-29 |
| 6871290 | Method for reducing a magnitude of a rate of current change of an integrated circuit | Tyler Thorp, Richard L. Wheeler, Brian Amick | 2005-03-22 |
| 6861885 | Phase locked loop design with diode for loop filter capacitance leakage current control | Pradeep Trivedi, Sudhakar Bobba | 2005-03-01 |
| 6850856 | I/O receiver thermal correction scheme | Shaishav Desai | 2005-02-01 |
| 6842057 | Analog state recovery technique for DLL design | Aninda Roy | 2005-01-11 |
| 6842351 | Method and apparatus for I/O resonance compensation | Aninda Roy, Brian Amick | 2005-01-11 |
| 6829548 | DLL static phase error measurement technique | Priya Ananthanarayanan, Pradeep Trivedi | 2004-12-07 |
| 6822345 | Chip/package resonance damping using controlled package series resistance | Brian Amick | 2004-11-23 |
| 6819192 | Jitter estimation for a phase locked loop | Brian Amick, Dean Liu, Pradeep Trivedi | 2004-11-16 |
| 6815986 | Design-for-test technique for a delay locked loop | Aninda Roy, Brian Amick, Dean Liu | 2004-11-09 |
| 6814485 | On-die thermal monitoring technique | Gin Yee | 2004-11-09 |
| 6812758 | Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generators | Pradeep Trivedi, Gin Yee | 2004-11-02 |
| 6812755 | Variation reduction technique for charge pump transistor aging | Gin Yee, Pradeep Trivedi | 2004-11-02 |
| 6809557 | Increasing power supply noise rejection using linear voltage regulators in an on-chip temperature sensor | Spencer Gold, Dean Liu, Kamran Zarrineh, Brian Amick, Pradeep Trivedi | 2004-10-26 |
| 6806698 | Quantifying a difference between nodal voltages | Brian Amick, Spencer Gold, Dean Liu, Kamran Zarrineh, Pradeep Trivedi | 2004-10-19 |
| 6803788 | SSTL voltage translator with dynamic biasing | Brian Amick, Lynn Warriner, Tri Tran | 2004-10-12 |
| 6791360 | Source synchronous interface using variable digital data delay lines | Brian Amick, Aninda Roy | 2004-09-14 |
| 6788045 | Method and apparatus for calibrating a delay locked loop charge pump current | Brian Amick, Pradeep Trivedi, Dean Liu | 2004-09-07 |
| 6784752 | Post-silicon phase offset control of phase locked loop input receiver | Brian Amick, Pradeep Trivedi, Dean Liu | 2004-08-31 |
| 6781355 | I/O power supply resonance compensation technique | Aninda Roy, Brian Amick | 2004-08-24 |
| 6778027 | Phase locked loop input receiver design with delay matching feature | Pradeep Trivedi, Brian Amick | 2004-08-17 |
| 6774665 | Cascode SSTL output buffer using source followers | Brian Amick, Lynn Warriner, Tri Tran | 2004-08-10 |
| 6774653 | Two-pin thermal sensor calibration interface | Spencer Gold, Kenneth House | 2004-08-10 |
| 6775638 | Post-silicon control of an embedded temperature sensor | Brian Amick, Spencer Gold, Pradeep Trivedi, Lynn Ooi | 2004-08-10 |