Issued Patents All Time
Showing 26–50 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8234478 | Using a data cache array as a DRAM load/store buffer | James Roberts, David B. Glasco, Peter B. Holmqvist, George R. Lynch, John H. Edmondson | 2012-07-31 |
| 8161267 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Gerald George Pechanek, Larry D. Larsen | 2012-04-17 |
| 8156404 | L2 ECC implementation | David B. Glasco, Peter B. Holmqvist, George R. Lynch, Karan Mehra, James Roberts | 2012-04-10 |
| 8135926 | Cache-based control of atomic operations in conjunction with an external ALU block | David B. Glasco, Peter B. Holmqvist, George R. Lynch, Karan Mehra, James Roberts | 2012-03-13 |
| 8131931 | Configurable cache occupancy policy | James Roberts, David B. Glasco, Peter B. Holmqvist, George R. Lynch, John H. Edmondson | 2012-03-06 |
| 8117357 | System core for transferring data between an external device and memory | Gerald George Pechanek, David Strube, Edwin Frank Barry, Charles W. Kurak, Jr., Carl Donald Busboom +6 more | 2012-02-14 |
| 8108610 | Cache-based control of atomic operations in conjunction with an external ALU block | David B. Glasco, Peter B. Holmqvist, George R. Lynch, Karan Mehra, James Roberts | 2012-01-31 |
| 8099650 | L2 ECC implementation | David B. Glasco, Peter B. Holmqvist, George R. Lynch, Karan Mehra, James Roberts | 2012-01-17 |
| 8060700 | System, method and frame buffer logic for evicting dirty data from a cache using counters and data types | David B. Glasco, Peter B. Holmqvist, George R. Lynch, James Roberts, John H. Edmondson | 2011-11-15 |
| 7961178 | Method and system for reordering isochronous hub streams | Robert A. Alfieri | 2011-06-14 |
| 7962667 | System core for transferring data between an external device and memory | Gerald George Pechanek, David Strube, Edwin Frank Barry, Charles W. Kurak, Jr., Carl Donald Busboom +6 more | 2011-06-14 |
| 7853779 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Gerald George Pechanek, Larry D. Larsen | 2010-12-14 |
| 7836317 | Methods and apparatus for power control in a scalable array of processor elements | Gerald George Pechanek, Edward A. Wolff | 2010-11-16 |
| 7809932 | Methods and apparatus for adapting pipeline stage latency based on instruction type | Edwin Franklin Barry, Gerald George Pechanek | 2010-10-05 |
| RE41012 | Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor | Edwin Franklin Barry, Gerald George Pechanek | 2009-11-24 |
| 7565490 | Out of order graphics L2 cache | Christopher D. S. Donham, John S. Montrym | 2009-07-21 |
| 7422675 | Process for changing anodes in an electrolytic aluminum production cell including adjustment of the position of the anode and device for implementing the process | Alain Van Acker | 2008-09-09 |
| 7386710 | Methods and apparatus for scalable array processor interrupt detection and response | Edwin Franklin Barry, Gerald George Pechanek, Larry D. Larsen | 2008-06-10 |
| 7340591 | Providing parallel operand functions using register file and extra path storage | Gerald George Pechanek, Larry D. Larsen | 2008-03-04 |
| 7266620 | System core for transferring data between an external device and memory | Gerald George Pechanek, David Strube, Edwin Franklin Barry, Charles W. Kurak, Jr., Carl Donald Busboom +6 more | 2007-09-04 |
| 7263624 | Methods and apparatus for power control in a scalable array of processor elements | Gerald George Pechanek, Edward A. Wolff | 2007-08-28 |
| D534481 | Tire tread | — | 2007-01-02 |
| 7058790 | Cascaded event detection modules for generating combined events interrupt for processor action | Edwin Franklin Barry, Gerald George Pechanek, Charles W. Kurak, Jr. | 2006-06-06 |
| 7024540 | Methods and apparatus for establishing port priority functions in a VLIW processor | Edwin Frank Barry, Edward A. Wolff, David Strube | 2006-04-04 |
| 6965991 | Methods and apparatus for power control in a scalable array of processor elements | Gerald George Pechanek, Edward A. Wolff | 2005-11-15 |