Issued Patents All Time
Showing 51–62 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7747897 | Method and apparatus for lockstep processing on a fixed-latency interconnect | Paul Racunas, George Z. Chrysos, Shubhendu Sekhar Mukherjee | 2010-06-29 |
| 7733898 | Method and apparatus for preventing starvation in a slotted-ring network | George Z. Chrysos, Yungho Choi | 2010-06-08 |
| 7624236 | Predictive early write-back of owned cache blocks in a shared memory computer system | George Z. Chrysos | 2009-11-24 |
| 7620791 | Mapping memory in a parallel processing environment | David Wentzlaff, Anant Agarwal | 2009-11-17 |
| 7620954 | Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors | Carl Ramey, Bongjin Jung, Judson S. Leonard | 2009-11-17 |
| 7558920 | Apparatus and method for partitioning a shared cache of a chip multi-processor | Antonio Juan-Hormigo, Joel S. Emer, Ramon Matas-Navarro | 2009-07-07 |
| 7551564 | Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect | — | 2009-06-23 |
| 7539141 | Method and apparatus for synchronous unbuffered flow control of packets on a ring interconnect | George Z. Chrysos, Stephen Felix | 2009-05-26 |
| 7461210 | Managing set associative cache memory according to entry type | David Wentzlaff, Anant Agarwal | 2008-12-02 |
| 7395381 | Method and an apparatus to reduce network utilization in a multiprocessor system | — | 2008-07-01 |
| 7240186 | System and method to avoid resource contention in the presence of exceptions | Shane Bell | 2007-07-03 |
| 6925552 | Method and system with multiple exception handlers in a processor | Matthew Reilly, Shane Bell, Chuan-Hua Chang | 2005-08-02 |