Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12019498 | Core off sleep mode with low exit latency | Thomas E. Dewey, Narayan Kulshrestha, Ramachandiran V, Sachin Satish Idgunji | 2024-06-25 |
| 11003238 | Clock gating coupled memory retention circuit | Anand Shanmugam Sundararajan, Ramachandiran V, Abhijeet Chandratre, Archana Srinivasaiah, Sachin Satish Idgunji | 2021-05-11 |
| 8432406 | Apparatus, system, and method for clipping graphics primitives with accelerated context switching | Vimal Parikh | 2013-04-30 |
| 7852341 | Method and system for patching instructions in a shader for a 3-D graphics pipeline | Christian Rouet, Rui M. Bastos | 2010-12-14 |
| 7714877 | Apparatus, system, and method for determining clipping distances | Vimal Parikh | 2010-05-11 |
| 7616218 | Apparatus, system, and method for clipping graphics primitives | Vimal Parikh, Andrew Tao | 2009-11-10 |
| 7542046 | Programmable clipping engine for clipping graphics primitives | Vimal Parikh, Andrew Tao | 2009-06-02 |
| 7490208 | Architecture for compact multi-ported register file | John W. Berendsen, Karim M. Abdalla, Rui M. Bastos, Radoslav Danilak | 2009-02-10 |
| 7439988 | Apparatus, system, and method for clipping graphics primitives with respect to a clipping plane | Vimal Parikh, Henry Packard Moreton | 2008-10-21 |
| 7420572 | Apparatus, system, and method for clipping graphics primitives with accelerated context switching | Vimal Parikh | 2008-09-02 |
| 7292254 | Apparatus, system, and method for clipping graphics primitives with reduced sensitivity to vertex ordering | Vimal Parikh, Andrew Tao | 2007-11-06 |
| 7224364 | Optimal initial rasterization starting point | James T. Battle | 2007-05-29 |
| 6581085 | Approximation circuit and method | Parin Bhadrik Dalal, Avery Li-Chun Wang | 2003-06-17 |
| 6507886 | Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory | Andrea Chen | 2003-01-14 |
| 6393512 | Circuit and method for detecting bank conflicts in accessing adjacent banks | Andrea Chen | 2002-05-21 |
| 6393534 | Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory | Andrea Chen | 2002-05-21 |
| 5036528 | Self-calibrating clock synchronization system | Duc N. Le, Cirillo L. Costantino, David P. Chengson, Aurangzeb Khan | 1991-07-30 |
| 5034964 | N:1 time-voltage matrix encoded I/O transmission system | Aurangzeb Khan, Robert W. Horst | 1991-07-23 |
| 4951050 | 2:1 Voltage matrix encoded I/O transmission system | Aurangzeb Khan | 1990-08-21 |