Issued Patents All Time
Showing 26–50 of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8700862 | Compression status bit cache and backing store | Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2014-04-15 |
| 8700883 | Memory access techniques providing for override of a page table | John S. Montrym | 2014-04-15 |
| 8627041 | Efficient line and page organization for compression status bit caching | Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts +2 more | 2014-01-07 |
| 8607008 | System and method for independent invalidation on a per engine basis | Lingfeng Yuan | 2013-12-10 |
| 8601235 | System and method for concurrently managing memory access requests | John S. Montrym, Lingfeng Yuan | 2013-12-03 |
| 8595437 | Compression status bit cache with deterministic isochronous latency | Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2013-11-26 |
| 8572206 | Transaction processing using multiple protocol engines | Charles Edward Watson, Jr., Rajesh Kota | 2013-10-29 |
| 8543792 | Memory access techniques including coalesing page table entries | Lingfeng Yuan | 2013-09-24 |
| 8539130 | Virtual channels for effective packet transfer | Dane T. Mrazek, Samuel H. Duncan, Patrick R. Marchand, Ravi Manyam, Yin Fung Tang +1 more | 2013-09-17 |
| 8504794 | Override system and method for memory access management | John S. Montrym, Lingfeng Yuan, Robert C. Keller | 2013-08-06 |
| 8504773 | Storing dynamically sized buffers within a cache | Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, James Roberts | 2013-08-06 |
| 8464001 | Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism | John H. Edmondson, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, James Roberts | 2013-06-11 |
| 8392667 | Deadlock avoidance by marking CPU traffic as special | Samuel H. Duncan, Wei-Je Huang, Atul Kalambur, Patrick R. Marchand, Dennis Ma | 2013-03-05 |
| 8359454 | Memory access techniques providing for override of page table attributes | John S. Montrym | 2013-01-22 |
| 8352709 | Direct memory access techniques that include caching segmentation data | John S. Montrym, Lingfeng Yuan | 2013-01-08 |
| 8347065 | System and method for concurrently managing memory access requests | John S. Montrym, Lingfeng Yuan | 2013-01-01 |
| 8347064 | Memory access techniques in an aperture mapped memory space | John S. Montrym | 2013-01-01 |
| 8327071 | Interprocessor direct cache writes | John M. Danskin, Emmett M. Kilgariff, Sean J. Treichler | 2012-12-04 |
| 8325194 | Mitigating main crossbar load using dedicated connections for certain traffic types | Dane T. Mrazek, Yongxiang Liu, Yin Fung Tang | 2012-12-04 |
| 8271734 | Method and system for converting data formats using a shared cache coupled between clients and an external memory | Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2012-09-18 |
| 8244984 | System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy | Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, James Roberts, John H. Edmondson | 2012-08-14 |
| 8234478 | Using a data cache array as a DRAM load/store buffer | James Roberts, Patrick R. Marchand, Peter B. Holmqvist, George R. Lynch, John H. Edmondson | 2012-07-31 |
| 8234458 | System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message | Brian K. Langendorf, Michael Brian Cox, Jonah M. Alben | 2012-07-31 |
| 8185602 | Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters | Charles Edward Watson, Jr., Rajesh Kota | 2012-05-22 |
| 8156404 | L2 ECC implementation | Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, Karan Mehra, James Roberts | 2012-04-10 |